Hard and soft failures are common in memory cells of resistive memory devices. Such failures are seen, for example, in magnetoresistive random access memory (MRAM), which is a non-volatile memory technology that uses magnetic elements. More specifically, MRAM comprises magnetic tunnel junction (MTJ) cells, which include a barrier layer separating a pinned layer and a free layer. The polarization of the free layer can be reversed by applying current in a specific direction such that the polarity of the pinned layer and the free layer are either substantially aligned or opposite. The resistance of the electrical path through the MTJ varies depending on the alignment of the polarizations of the pinned and free layers. This variation in resistance can be used to program and read the MTJ cells, as is known in the art.
The barrier layer is typically a thin insulating layer formed from materials such as, MgO, which is susceptible to breakdowns. Particularly, the barrier layer can easily breakdown under relatively small stress levels as device technology advances and the size of MTJ cells shrink. Such breakdown can lead to hard failures which cannot be easily repaired due to permanent or long term damage, as opposed to soft failures which are easily repairable.
In particular, irreparable or hard failures require replacement of failed cells. However, it is not feasible to replace individual bit cells in memory arrays once the memory arrays have been packaged. Thus, rather than replace an entire memory array due to failed bit cells, hard failures are typically dealt with using replacement rows (or columns). In more detail, failure bits of a memory array are first detected; for example, a test macro is run on the memory array to detect failed bit cells. The rows (and/or columns) where the failed bit cells lie, are noted, for example, in a one-time programmable (OTP), and typically, non volatile memory (NVM) array, which is external to the memory array. The OTP NVM array holds information regarding failed rows which comprise failed bit cells.
Replacement rows are then provided for the failed rows. These replacement rows are replicas of entire failed rows, but with failed bit cells replaced with healthy or correctly functioning bit cells. The replacement rows are usually rows of the memory array which have been requisitioned for storing replicas of failed rows in the remainder of the memory array. Since the OTP NVM access time is slow, in practice, the information regarding the failed rows is loaded into fast registers, for example, magnetoresistive random access memory (MRAM) internal registers upon system power up. Thus, every time a memory access is attempted on the memory array, the MRAM internal registers are checked to see if the memory access address is contained therein, in order to ascertain if the desired memory access row is a failed row. If the purported memory access corresponds to a failed row, then the memory access address is rerouted to an address where a corresponding replacement row for the failed row is provided in the memory array. Thus, instead of the failed row, the corresponding replacement row is selected for the memory access.
The above techniques are also extended where ports of the memory array may be damaged, rather than bit cells. For example, if an input/output (TO) port of the memory array is detected to have failed, a replacement IO (or “RIO”) is provided. Access addresses which may have required access through a failed IO port are re-routed to a replacement IO. In more detail, in one known implementation, the OTP NVM may be configured to either store a replacement IO for an entire failed IO, such that a replacement IO is obtained from the internal MRAM register, as above, in case a desired access pertains to the failed IO. In another known implementation, the OTP NVM may be configured to store replacement IO information in segments, wherein the memory array may be divided into a plurality of segments (say, n equal segments, for example), with each of the n segments comprising multiple rows. The replacement IO information is created for each of the n segments, such that replacement IO for a particular segment m pertains to failed IO within that segment m. Thus, if segment m has a failed IO, and the desired memory access address falls under segment m, then the corresponding replacement IO can be retrieved only for segment m, rather than retrieving an entire replacement IO. Accordingly, this implementation requires only 1/n of the replacement IO space that is consumed in the OTP NVM, as compared to the previous implementation which stores the entire replacement IO.
Regardless of specific implementations for the OTP NVM that are chosen, the above conventional techniques for dealing with failed bit cells or IOs are deficient in several aspects. Firstly, these techniques are slow and time consuming; and moreover, such techniques cannot be performed on the fly. This is because such techniques require multiple memory array accesses, since at most one row can be accessed at one time in typical memory array designs, and the process of attempting to access a failed row, going through the internal MRAM registers, and then accessing the replacement row or replacement IO incurs multiple clock cycles or in other words, high latency. Secondly, the replacement rows and/or replacement IOs consume valuable space on the memory array, and therefore, the number of replacement rows is typically restricted, thus imposing a restriction on the number of failed rows and/or failed IOs which can be effectively dealt with. Thus, not only are the conventional techniques slow, and unfit for real time repair of failures, the conventional techniques can also lead to inaccuracies where valid replacement rows and/or replacement IOs cannot be provided for all failures.